Published Papers - SPICE Parameter Extraction

The full text of most of these papers may be found at the IEEE website at www.ieee.org.

X. -H. Du and B. Sheu
"Modeling ferroelectric capacitors for memory applications"
"IEEE Circuits and Devices Magazine, Volume 18, Issue 6, November 2002, Pages 10-16."

"S. Lee, C. S. Kim, H. K. Yu"
"Improved BSIM3v3 model for RF MOSFET IC simulation"
"Electronics Letters, Volume 36, Issue 21, 12 October 2000, Pages 1818-1819."

Y. Iino (Silvaco Japan)
"A trial report: HiSIM-1.2 parameter extraction for 90 nm technology"
"2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004, Volume 2, 2004 NSTI Nanote

"M. N. Marbell, S. V. Cherepko, A. Madjar, J. C. M. Hwang, M. Frei, M. A. Shibib"
"An improved large-signal model for harmonic-balance simulation of Si LD-MOSFETs"
"Conference Proceedings - European Microwave Conference, Volume 1, 2004, Pages 225-228. "

"S.-H. Lee, J. â•„Y. Lee, S. -Y. Lee, C. W. Park, H. -C. Bae, J. -Y. Kang"
"VBIC model application and model parameter optimization for sige HBT"
"Electrochemical Society Proceedings, Volume 7, 2004, Pages 385-394. "

"W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury"
"Low current application dedicated process characterization method"
"IEEE International Conference on Microelectronic Test Structures, 2002, Pages 41-44."

"S. V. Cherepko, M. S. Shirokov, J. C. M. Hwang, A. Brandstaedter"
"Improved large-signal model and model extraction procedure for InGaP/GaAs HBTs under high-current operations"
"IEEE MTT-S International Microwave Symposium Digest, Volume 2, 2001, Pages 671-674."

"P. R. Palmer, J. C. Joyce, P. Y. Eng, J. Hudgins, E. Santi, R. Dougal"
"Circuit simulator models for the diode and IGBT with full temperature dependent features"
"PESC Record - IEEE Annual Power Electronics Specialists Conference, Volume 4, 2001, Pages 2171-2177

"A. A. Keshavarz, J. L. Walters, R. K. Sampson"
"Mobility degradation and current loss due to vertical electric field in channel area of submicron MOS devices"
"2000 International Conference on Modeling and Simulation of Microsystems - MSM 2000, 2000, Pages 34

Lee S. Kim C.S. Yu H.K.
"Improved SPICE Modelling and Parameter Extraction for RF MOSFETs"
Proc. ESSDERC 2001.

T. Myono, E. Nishibe, S. Kikuchi and et al.,
"Modeling and parameter extraction technique for uni-directional HV MOS devices"
IEICE T. Fund. Electr., Volume E83A, Mar. 2000, Pages 412-420.

T. Myono, E. Nishibe, S. Kikuchi and et al.,
"High-voltage MOS device modeling with BSIM3v3 SPICE model"
IEICE Trans. Electronics, Volume E82C, Apr. 1999, Pages 630-637.

Arun N. Lokanathan, Jay B. Brockman
"Process Multi-Circuit Optimization"
Proceedings of the 35th IEEE Conference on Design Automation, 15-19 Jun 1998, pp. 382-387.

Eric Vandenbossche, Georege Kopalidis, Marnix Tack and Wim Schoenmaker
"Statistical Modeling based on extensive TCAD simulations Proposed methodology for extraction of Fast/Slow models and Statistical models"
Proc. SISPAD, 1998, pp.85-88.

M. A. Imam, M .A. Osman and A. A. Osman,
"MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model"
IEEE Trans. Computer-Aided Design, Volume 15, Apr. 1996, Pages 446-451.

R. Clancy, M. Welten, J. A. Power, B. Mason, P. Stribley and A. Mathewson
"A comparison of RS/1 and SPAYN for the generation of worst-case SPICE level 3 MOSFET model parameters"
IEE Colloquium on Improving the Efficiency of IC Manufacturing Technology, 1995, pp. 7/1 -7/4.

M.Welten et al
"Enhanced Worst-Case Simulation Utilising Regression based performance spread"
Proc ESSDERC 95, The Hague, Netherlands, pp.761-764.

J.Power et al
"Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design"
IEEE Trans. on Semiconductor manufacturing, Vol.7 August 1994, pp306-318.

Clancy, Welton, Wall, Power, Mason, Stribley, Mathewson
"Statistical Worst-Case Analysis Techniques for CMOS Technology Using Design of Experiments"

K.Burke et al
"Worst-Case MOSFET Parameter Extraction for a 2um CMOS Process"
Proc. IEEE 1994 ICMTS, Vol. 7 pp119-125.

Power, Donnellan, Burke, Moloney, Mathewson, Lane
"Generation of MOS Model Parameters Covering Statistical Process Variations"
ESSDERC, 1993.

Power, Mathewson, Lane
"An Approach for Relating Model Parameter Variabilities to Process Fluctuations"
IEEE ICMTS, 1993.

Power, Barry, Mathewson, Lane
"Accurate and Efficient Predictions of Statistical Circuit Performance Spreads"
IEEE CICC, 1992.

Power, Lane
"An Enhanced SPICE MOSFET Model Suitable for Analog Applications"
IEEE Trans CAD, 1992.

Power, Clancy, Wall, Mathewson, Lane
"An Investigation of MOSFET Statistical and Temperature Effects"
IEEE ICMTS, 1992.

Power, Mathewson, Lane
"MOSFET Statistical Parameter Extraction Using Multivariate Statistics"
IEEE ICMTS, 1991.

Power, Barry, Mathewson, Lane
"Worst-Case Simulation Using Principal Component Analysis Techniques: An Investigation"
ESSDERC, 1991.

Lin, Kuh, Marek-Sadowska
"Stepwise Equivalent Conductance Circuit Simulation Technique"
UC Berkeley, CA.

Lin, Mark-Sadowska, Kuh
"SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI"
UC Berkeley, CA.

Power, Lane
"Enhanced SPICE MOSFET Model for Analog Applications"
IEEE ICMTS, 1990.