SmartSpice

The full text of most of these papers may be found at the IEEE website at www.ieee.org.

Moon Hyo Kang, Ji Ho Hur, Youn Duck Nam, Eun Ho Lee, Se Hwan Kim and Jin
Jang
"An optical feedback compensation circuit with a-Si:H thin-film transistors for active matrix organic light emitting diodes", Journal of Non-Crystalline Solids, In Press, Corrected Proof, Available online 5 February 2008.

Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch,
Yasuaki Inoue,
"A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2,"
IEEJ Transactions on Electrical and Electronic
Engineering Vol. 3, Issue 1, Jan. 2008, pp. 64-71.

Y. Iino, I. Pesic,
"HiSIM- Replacement of BSIM4 in UDSM circuit simulations,"
2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007,
Technical Proceedings, Vol. 3, 2007 NSTI Nanotechnology Conference and Trade
Show - NSTI Nanotech 2007, Technical Proceedings, 2007, pp. 682-683.

Y. S. Yu
"A multi-gate single-electron transistor model for circuit simulations by SPICE", Journal of the Korean Physical Society, Volume 50, No. 3, March 2007, Pages 739-743.

Y. S. Yu, S. W. Hwang, D. Ahn
"Transient modelling of single-electron transistors for efficient circuit simulation by SPICE"
IEE Proceedings: Circuits, Devices and Systems, Volume 152, Issue 6, December 2005, Pages 691-696.

S. Mahapatra, A. M. Ionescu
"Realization of multiple valued logic and memory by hybrid SETMOS architecture"
IEEE Transactions on Nanotechnology, Volume 4, Issue 6, November 2005, Pages 705-714.

X. Guo, S. R. P. Silva
"Investigation on the current nonuniformity in current-mode TFT active-matrix display pixel circuitry"
IEEE Transactions on Electron Devices, Volume 52, Issue 11, November 2005, Pages 2379-2385.

K. Degawa, T. Aoki, H. Inokawa, T. Higuchi, Y. Takahashi
"A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors"
Proceedings of The International Symposium on Multiple-Valued Logic pp. 32-38.

C. Alaoui and Z. M. Salameh
"A novel thermal management for electric and hybrid vehicles"
IEEE Transactions on Vehicular Technology, Volume 54, Issue 2, March 2005, Pages 468-476.

Katsuhiko Nishiguchi, Hiroshi Inokawa, Yukinori Ono, Akira Fujiwara, and Yasuwo Takahashi
"Multifunction Boolean Logic Using Single-Electron Transistors."
IEICE Trans. Electron. Vol E87 -C , No.11 November 2004

S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee, A. M. Ionescu
"Analytical modelling of single electron transistor for hybrid CMOS-SET analog IC design"
IEEE Transactions on Electron Devices, Volume 51, Issue 11, November 2004, Pages 1772-1782.

H. Inokawa, Y. Takahashi, K. Degawa, T. Aoki, T. Higuchi
"A simulation methodology for single-electron multiple-valued logics and its application to a latched parallel counter"
IEICE Transactions on Electronics, Volume E87-C, Issue 11, November 2004, Pages 1818-1826.

K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, Y. Takahashi
"A single-electron-transistor logic gate family for binary, multiple-valued and mixed-mode logic"
IEICE Transactions on Electronics, Volume E87-C, Issue 11, November 2004, Pages 1827-1836.

X. Guo and S. R. P. Silva
"Circuit simulation of current-modulated field emission display pixel driver based on carbon nanotubes"
Electronics Letters, Volume 40, Issue 18, September 2004, Pages 1113-1115.

A. M. Ionescu, S. Mahapatra, V. Pott
"Hybrid SETMOS architecture with Coulomb Blockade oscillations and high current drive"
IEEE Electron Device Letters, Volume 25, Issue 6, June 2004, Pages 411-413.

A. Rahman and V. Polavarapuv
"Evaluation of low-leakage design techniques for field programmable gate arrays"
CM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Volume 12, 2004, Pages 23-30.

H. Inokawa, Y. Takahashi, K. Degawa, T. Aoki, T. Higuchi
"A single-electron-transistor logic gate family and its application - Part II: Design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions"
Proceedings of The International Symposium on Multiple-Valued Logic 2004, Pages 269-274.

S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, A. M. Ionescu
"SETMOS: A Novel True Hybrid SET- CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog Ics"
Technical Digest - International Electron Devices Meeting, 2003, Pages 703-706.

S. Mahapatra, K. Banerjee, F. Pegeon, A. M. Ionescu
"A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits"
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 2003, Pages 497-502.

H. Inokawa and Y. Takahashi
"Experimental and simulation studies of single-electron-transistor-based multiple-valued logic"
Proceedings of The International Symposium on Multiple-Valued Logic, 2003, Pages 259-266.

A. L. Sternberg, L. W. Massengill, S. Buchner, R. L. Pease, Y. Boulghassoul, M. W. Savage, D. McMorrow, R. A. Weller
"The role of parasitic elements in the single-event transient response of linear circuits"
IEEE Transactions on Nuclear Science, Volume 49 I, Issue 6, December 2002, Pages 3115-3120.

A. L. Sternberg, L. W. Massengill, R. D. Schrimpf, P. Calvel
"Application determinance of single-event transient characteristics in the LM111 comparator"
IEEE Transactions on Nuclear Science, Volume 48, Issue 6 I, December 2001, Pages 1855-1858.

J. -J. Wang, R. B. Katz, F. Dhaoui, J. L. McCollum, W. Wong, B. E. Cronquist, R. T. Lambertson, E. Hamdy, I. Kleyner, W. Parker
"Clock buffer circuit soft errors in antifuse-based field programmable gate arrays"
IEEE Transactions on Nuclear Science, Volume 47, Issue 6 III, December 2000, Pages 2675-2681.

K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. -I Takagi, A. Toriumi
"Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits"
Japanese Journal of Applied Physics, Part 2: Letters, Volume 39, Issue 4 B, 2000, Pages 2321-2324.

Pruvost, B.; Mizuta, H.; Oda, S
"3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs"
Nanotechnology, IEEE Transactions on Volume 6, Issue 2, March 2007 Page(s): 218 - 224