HyperFault Mixed-Level Fault Simulator is a Verilog IEEE-1364-2001 compliant fault simulator that analyses test vectors' ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing. HyperFault's proven algorithms enable efficient multi-pass fault simulation over distributed CPUs to achieve accurate results with excellent runtime performance.

Download full presentation. (1.33Mb pdf - 14 pages)