| SmartSpice BSIM3 v3 Intrinsic Capacitance Models | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
UC Berkeley released the final version of the BSIM3v3 model in October, 1995. This model is now available in SmartSpice 1.4.0 in two different variants. The SmartSpice implementation is referred to as MOSFET model level 8. The original Berkeley model is also available within SmartSpice as MOSFET model level 81. This model was included within SmartSpice with only one change: it allows output of the partial derivatives of the terminal charges with respect to terminal voltages. This application note describes the BSIM3v3 Capacitance Models, and their verification using Silvaco's two dimensional device simulator, ATLAS.
For further information regarding the BSIM3v3 Level 8 implementation, see Application Notes :
SECTION
1 The following model parameters are used in Intrinsic and Extrinsic Capacitance Models.
Table 1: Capacitance model parameters. Notes :
SECTION
2
The capacitance model in the SmartSpice BSIM3v3
(level 8) model is evaluated in three steps.
|
| Variable | Definition | Variable | Definition |
|---|---|---|---|
| capbd | Bulk-drain capacitance | qg | Total gate charge |
| capbs | Bulk-source capacitance | cqg | Gate capacitance current |
| capgbo | Gate-bulk overlap capacitance | qd | Total drain charge |
| capgso | Gate-source overlap capacitance | cqd | Drain capacitance current |
| capgdo | Gate-drain overlap capacitance | cggb (cgg) | Charge conservation model term |
| capgg | Total gate capacitance | cgdb (cgd) | Charge conservation model term |
| qbulk | Channel bulk charge | cgsb (cgs) | Charge conservation model term |
| qgate | Channel gate charge | cdgb (cdg) | Charge conservation model term |
| qdrain | Channel drain charge | cddb (cdd) | Charge conservation model term |
| qbd | Bulk-drain charge | cdsb (cds) | Charge conservation model term |
| qbs | Bulk-source charge | cbgb (cbg) | Charge conservation model term |
| qb | Total bulk charge | cbdb (cbd) | Charge conservation model term |
| cqb | Bulk capacitance current | cbsb (cbs) | Charge conservation model term |
Table 2: Charge and Capacitance Output Variables for BSIM3v3 Model.
Capacitances listed in Table 2 are used in .AC analysis. The BSIM3v3 capacitance matrix used in all types of simulation in the frequency domain is shown in Table 3 (the NQS model contribution to the capacitance matrix is not reflected in Table 3).
| Node | Gate | Drain | Source | Bulk |
|---|---|---|---|---|
| Gate | +cggb +capgdo +capgso +capgbo |
+cgdb -capgdo |
+cgsb -capgso |
-cggb -cgdb -cgsb -capgbo |
| Drain | +cdgb -capgdo |
+cddb +capgdo +capbd |
+cdsb | -cdgb -cddb -cdsb -capbd |
| Source | -cggb -cdgb -cbgb -capgso |
-cgdb -cddb -cbdb |
-(cgsb+cdsb+cbsb) +capgso +capbs |
(*) -capbs |
| Bulk | +cbgb -capgbo |
+cbdb -capbd |
+cbsb -capbs |
-(cbgb+cbdb+cbsb) +capgbo +capbd+capbs |
Table 3: BSIM3v3 capacitance matrix for .AC analysis
SECTION
3
40/60 Charge Partitioning
The input deck "Test: CAPMOD = 1 XPART = 0.4
(40/60)" contains two N-channel transistors MN1 and MN2.
The first one references the model nmos1 with CAPMOD = 1, and the second references nmos2 with CAPMOD = 2. In both models the 40/60 Drain/Source charge partition is defined by XPART = 0.4.
The option CAPDC = 1 is set to calculate charges and capacitances during .DC analysis. The stored device parameters are listed in the .SAVE statement. The .LET statement is used to calculate the source charge "qsource" of the transistor MN1.
The gate voltage VGG is swept from -2 to 8 in increments of 0.2. The drain to source voltage is defined by VDD = 1.
Input Deck
***** Test: CAPMOD=1 XPART=0.4 ( 40/60) * UC Berkeley Intrinsic Capacitance model * from * http://rely.eecs.berkeley.edu:8080/bsim3www/ftp/Modelcards/modelcard.nmos .OPTIONS CAPDC=1 .OPTIONS GMIN=1e-17 ABSTOL=1e-16 VNTOL=1e-9 .OPTIONS RELTOL=1e-4 NOMOD .SAVE @mn1[vth] @mn1[vdsat] @mn1[gm] + @mn1[qgate] @mn1[qdrain] @mn1[qbulk] + @mn1[cggb] @mn1[cgdb] @mn1[cgsb] @mn1[cdgb] @mn1[cddb] + @mn1[cdsb] @mn1[cbgb] @mn1[cbdb] @mn1[cbsb] + @mn2[vth] @mn2[vdsat] @mn2[gm] + @mn2[cggb] @mn2[cgdb] @mn2[cgsb] @mn2[cdgb] @mn2[cddb] + @mn2[cdsb] @mn2[cbgb] @mn2[cbdb] @mn2[cbsb] .LET qsource='-@mn1[qgate]-@mn1[qdrain]-@mn1[qbulk]' .DC VGG -2 8 0.2 VDD DD 0 dc 1 VGG GG 0 dc 0 VBB bb 0 dc 0 * **************** CAPMOD=1 vb b bb DC 0 vd d DD DC 0 vs s 0 DC 0 vin g GG dc 0 MN1 d g s b nmos1 w=4.0u l=0.8u ** **************** CAPMOD=2 vb2 b2 bb DC 0 vd2 d2 DD DC 0 vs2 s2 0 DC 0 vin2 g2 GG dc 0 MN2 d2 g2 s2 b2 nmos2 w=4.0u l=0.8u *model = bsim3v3 Capacitance Model CAPMOD=1 *Berkeley Spice Compatibility * Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 .MODEL nmos1 nmos LEVEL=8 +Tnom=27.0 + CAPMOD=1 XPART=0.4 +Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 +Lint=9.36e-8 Wint=1.47e-7 +Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 +Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 +Nlx= 3.52291E-08 W0= 1.163e-6 +K3b= 2.233 +Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 +Rdsw= 650 U0= 388.3203 wr=1 +A0= .3496967 Ags=.1 B0=0.546 B1= 1 + Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 +Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 +Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 +Cdsc=-2.147181E-05 +Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 + Cdscd = 0 Prwg = 0 +Eta0= 1.0281729E-02 Etab=-5.042203E-03 +Dsub= .31871233 +Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 +Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 +Pvag= 0 delta=0.01 + Wl = 0 Ww = -1.420242E-09 Wwl = 0 + Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 + Lw = 0 Lwl = 0 Lln = .316394 Lwn = 0 +kt1=-.3 kt2=-.051 At= 22400 Ute=-1.48 +Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 +Kt1l=0 Prt=764.3 ********* Capacitance Model CAPMOD=2 .MODEL nmos2 nmos LEVEL=8 +Tnom=27.0 + CAPMOD=2 XPART=0.4 +Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 +Lint=9.36e-8 Wint=1.47e-7 +Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 +Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 +Nlx= 3.52291E-08 W0= 1.163e-6 +K3b= 2.233 +Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 +Rdsw= 650 U0= 388.3203 wr=1 +A0= .3496967 Ags=.1 B0=0.546 B1= 1 + Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 +Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 +Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 +Cdsc=-2.147181E-05 +Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 + Cdscd = 0 Prwg = 0 +Eta0= 1.0281729E-02 Etab=-5.042203E-03 +Dsub= .31871233 +Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 +Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 +Pvag= 0 delta=0.01 + Wl = 0 Ww = -1.420242E-09 Wwl = 0 + Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 + Lw = 0 Lwl = 0 Lln = .316394 Lwn = 0 +kt1=-.3 kt2=-.051 At= 22400 Ute=-1.48 +Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 +Kt1l=0 Prt=764.3 END
Simulation Results for 40/60
The SmartSpice simulation results are shown in Fig.1, Fig.2 and Fig.4.
The intrinsic model terminal charges @mn1[qbulk], @mn1[qdrain], @mn1[qgate] and qsource are shown in Fig.1. The drain to source charge partition in the saturation region ( 0.6 < vgg < 2.2 ) corresponds to XPART = 0.4.
Figure 1 : Gate, drain, source and bulk charges for XPART = 0.4
The intrinsic model transcapacitances are shown in Fig.2. The transcapacitances modeled by ATLAS are shown in Fig.3.
Notes :
- Transcapacitances modeled by ATLAS include overlap capacitances, while the SmartSpice transcapacitances shown in Fig.2 are purely intrinsic.
- The ATLAS transcapacitances are plotted with opposite signs.
Figure 2 : Intrinsic model transcapacitances
Figure 3: Transcapacitances modeled by ATLAS
The BSIM3v3 capacitance curve shapes are in good agreement with those produced by ATLAS. However, four BSIM3v3 transcapacitances cbsb, cddb, cgdb and cgsb change signs while the gate voltage is changing from -2 to 8. These transcapacitances of the transistors MN1 and MN2 calculated for CAPMOD = 1 and CAPMOD = 2 respectively are shown in Fig.4.
Figure 4: Intrinsic transcapacitances with CAPMOD = 1 and CAPMOD = 2
The shapes of the transcapacitance curves for CAPMOD = 2 are smoother, however the sign changes take place for both CAPMOD values as follows :
- cddb and cdgb change signs in saturation,
- cbsb changes sign in linear,
- cgsb changes sign in subthreshold region.
SECTION
4
0/100 Charge Partitioning
The input deck "Test: CAPMOD = 1 XPART = 1
( 0/100)" contains two N-channel transistors MN1 and MN2. The first
one references the nmos8 SmartSpice Level 8 model, and the second
references the nmos81 UC Berkeley Level 81. In both models the 0/100
Drain/Source charge partition is defined by XPART = 1.
The option CAPDC = 1 is set to calculate charges and capacitances during .DC analysis. The stored device parameters are listed in the .SAVE statement. The first .LET statement is used to calculate the source charge "qsource" of the transistor MN1.This statement is followed by eight .LET statements used to calculate numerical derivatives of charges with respect to the gate and drain voltages.
The first .DC statement sweeps the gate voltage VGG from -2 to 8 in increments of 0.01. The drain to source voltage is defined by VDD = 1. The second .DC statement sweeps the drain voltage VDD from 0 to 6 in increments of 0.01. The gate to source voltage is defined by VGG = 5. Input Deck
***** Test: CAPMOD=1 XPART=1 ( 1/100) * UC Berkeley Intrinsic Capacitance model * from * http://rely.eecs.berkeley.edu:8080/bsim3www/ftp/Modelcards/modelcard.nmos .OPTIONS CAPDC=1 .OPTIONS GMIN=1e-17 ABSTOL=1e-16 VNTOL=1e-9 .OPTIONS RELTOL=1e-4 NOMOD .SAVE @mn1[vth] @mn1[vdsat] @mn1[gm] + @mn1[qgate] @mn1[qdrain] @mn1[qbulk] + @mn1[cggb] @mn1[cgdb] @mn1[cgsb] @mn1[cdgb] @mn1[cddb] + @mn1[cdsb] @mn1[cbgb] @mn1[cbdb] @mn1[cbsb] + @mn2[vth] @mn2[vdsat] @mn2[gm] + @mn2[cggb] @mn2[cgdb] @mn2[cgsb] @mn2[cdgb] @mn2[cddb] + @mn2[cdsb] @mn2[cbgb] @mn2[cbdb] @mn2[cbsb] .LET qsource='-@mn1[qgate]-@mn1[qdrain]-@mn1[qbulk]' .LET num_cggb='deriv(@mn1[qgate])' .LET num_cdgb='deriv(@mn1[qdrain])' .LET num_csgb='deriv(qsource)' .LET num_cbgb='deriv(@mn1[qbulk])' .LET num_cgdb='deriv(@mn1[qgate])' .LET num_cddb='deriv(@mn1[qdrain])' .LET num_csdb='deriv(qsource)' .LET num_cbdb='deriv(@mn1[qbulk])' .DC VGG -2 8 0.01 .DC VDD 0 6 0.01 VDD DD 0 dc 1 VGG GG 0 dc 5 VBB bb 0 dc 0 * **************** Level 8 vb b bb DC 0 vd d DD DC 0 vs s 0 DC 0 vin g GG dc 0 MN1 d g s b nmos8 w=4.0u l=0.8u ** **************** Level 81 vb2 b2 bb DC 0 vd2 d2 DD DC 0 vs2 s2 0 DC 0 vin2 g2 GG dc 0 MN2 d2 g2 s2 b2 nmos81 w=4.0u l=0.8u ********** model = bsim3v3 Level 8 *Berkeley Spice Compatibility * Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 .MODEL nmos8 nmos LEVEL=8 +Tnom=27.0 + CAPMOD=1 XPART=1 +Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 +Lint=9.36e-8 Wint=1.47e-7 +Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 +Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 +Nlx= 3.52291E-08 W0= 1.163e-6 +K3b= 2.233 +Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 +Rdsw= 650 U0= 388.3203 wr=1 +A0= .3496967 Ags=.1 B0=0.546 B1= 1 + Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 +Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 +Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 +Cdsc=-2.147181E-05 +Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 + Cdscd = 0 Prwg = 0 +Eta0= 1.0281729E-02 Etab=-5.042203E-03 +Dsub= .31871233 +Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 +Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 +Pvag= 0 delta=0.01 + Wl = 0 Ww = -1.420242E-09 Wwl = 0 + Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 + Lw = 0 Lwl = 0 Lln = .316394 Lwn = 0 +kt1=-.3 kt2=-.051 At= 22400 Ute=-1.48 +Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 +Kt1l=0 Prt=764.3 * ********** model = bsim3v3 Level 81 .MODEL nmos81 nmos LEVEL=81 +Tnom=27.0 + CAPMOD=1 XPART=1 +Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 +Lint=9.36e-8 Wint=1.47e-7 +Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 +Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 +Nlx= 3.52291E-08 W0= 1.163e-6 +K3b= 2.233 +Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 +Rdsw= 650 U0= 388.3203 wr=1 +A0= .3496967 Ags=.1 B0=0.546 B1= 1 + Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 +Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 +Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 +Cdsc=-2.147181E-05 +Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 + Cdscd = 0 Prwg = 0 +Eta0= 1.0281729E-02 Etab=-5.042203E-03 +Dsub= .31871233 +Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 +Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 +Pvag= 0 delta=0.01 + Wl = 0 Ww = -1.420242E-09 Wwl = 0 + Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 + Lw = 0 Lwl = 0 Lln = .316394 Lwn = 0 +kt1=-.3 kt2=-.051 At= 22400 Ute=-1.48 +Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 +Kt1l=0 Prt=764.3 .endSimulation Results for 0/100
The SmartSpice simulation results for XPART = 1 are shown in Fig5, Fig.6 and Fig.7.
The intrinsic model terminal charges @mn1[qbulk], @mn1[qdrain], @mn1[qgate] and qsource are shown in Fig.5. The drain to source charge partition in the saturation region ( 0.6 < vgg < 2.2 ) corresponds to the 0/100 partition.
Figure 5: Gate, drain, source and bulk charges for XPART = 1
The intrinsic model transcapacitances are shown in Fig.6 for both SmartSpice Level 8 and UC Berkeley Level 81.
Figure 6: Intrinsic model transcapacitances for XPART = 1
The analytically calculated BSIM3v3 transcapacitances are verified using the numerically computed ones in Fig.6 and Fig.7. As can be seen, the 0/100 simulation results do not match the ATLAS results as well as 40/60. The total intrinsic drain capacitance cddb demonstrates an unexpected behavior by exceeding the value Cox * W * L in the linear region.
Figure 7: Intrinsic model transcapacitances for XPART = 1 vs VDD
