UC Berkeley released the final version of the BSIM3v3 model in October, 1995. This model is now available in SmartSpice 1.4.0 in two different variants. The SmartSpice implementation is referred to as MOSFET model level 8. The original Berkeley model is also available within SmartSpice as MOSFET model level 81. Both models produce virtually identical results when commonly acceptable model param- eter sets are used. However, these models are not identical since the SmartSpice implementation provides a number of additional parameters currently not supported in Berkeley Spice.

This application note describes the SmartSpice BSIM3v3 implementation and the primary differences between SmartSpice level 8 and level 81 models.

• Section 1 contains a list of standard SmartSpice MOSFET model parameters not supported in Berkeley Spice
• Section 2 lists the level 8 and level 81 parameters with the same names but different default values.
• Section 3 describes additional SmartSpice level 8 parameters introduced in order to improve the Berkeley BSIM3v3 model.
• Section 4 contains a list of the BSIM3v3 output parameters that can be printed, plotted and mea- sured during simulation.
• Section 5 describes the capacitance model in the SmartSpice implementation of the BSIM3v3 model.
• Section 6 contains an example input deck, illustrating some aspects of the BSIM3v3 model

SECTION 1
Standard SmartSpice MOSFET Parameters

The following model parameters are standard in all SmartSpice MOSFET models. They are used in the SmartSpice implementation of both version 2 (level 7) and 3 (level 8) of the BSIM3 model. The parameter names and defaults are identical for both versions.

Table 1: Standard SmartSpice MOSFET parameters.

The options listed below are applied to the SmartSpice BSIM3v3 Level 8 model. These parameters can be specified in the .OPTIONS statement.

The options ACM, DEFL, DEFW, DEFAD, DEFAS, DEFPD, DEFPS, DEFNRD, DEFNRS, HDIF, LD, LDIF, SCALE, SCALM and TNOM are standard for all MOSFET models including BSIM3v3 Level 8.

The option BYPASS currently is unsupported for BSIM3v3.

The option CAPDC = 1 can be specified to calculate BSIM3v3 capacitances for both Level 8 and Level 81. Default 0 (OFF).

The option CONV = num ( 0 =< num <= 5 ) is supported for BSIM3v3. Default 0.

The conductance GMIN is connected in parallel with the bulk-drain and bulk-source diodes. Default 1e-12.

The conductance DCGMIN is connected between drain and source nodes. Default 0.

The option VZERO = num is applied to the BSIM3v3 Level 8 model. This option defines the MNA formulation in SmartSpice. The option VZERO = 2 is recommended when simulating relatively large circuits, with hundreds or thousands of transistors in the time domain. It accelerates simulation and in some cases increases the accuracy of simulation results. Default 0. For further information regarding the option VZERO, see "SmartSpice Version 1.4.0 Release Notes".

The option EXPERT = 1 can be used to detect discontinuities in the BSIM3v3 model. If EXPERT = 777 SmartSpice will detect negative conductances GM, GDS and GMBS, and negative capacitances. Default 0 (OFF).

For further information regarding the BSIM3v3 Level 8 implementation, see Application Notes: 1. "SmartSpice BSIM3 Version 3 Intrinsic Capacitance Models" 2. "SmartSpice BSIM3 Version 3 Non-Quasi Static Model"

The following junction current and capacitance parameters have different defaults in the SmartSpice (level 8) and Berkeley (level 81) BSIM3v3 models.

Note : In the UC Berkeley implementation, the drain saturation current is calculated as follows;

    if AD > 0 then
        DrainSatCurrent = JS * AD
    else
        DrainSatCurrent = 1.0e-14
	

The parameters IS and JSW are not used.

Additional parameters were introduced into the SmartSpice level 8 model to resolve conflicting situations in the Berkeley BSIM3v3 implementation, and to improve the convergence properties of the BSIM3v3 model.

3.1 TEMPMOD Parameter

The UC Berkeley BSIM3v3 manual (final version) and implementation are not consistent in terms of the ni, fs and vbi temperature dependencies. In the source code they are calculated as functions of the nominal temperature tnom. In contrast the BSIM3v3 manual treats them as functions of the circuit temperature, temp.

In the SmartSpice level 8 model, ni, fs and vbi are calculated at tnom by default. This corresponds to the Berkeley implementation rather that the documentation. The temperature equations described in the Berkeley manual will be used if the model parameter tempmod=2.

3.2 Parameter Scaling

In the UC Berkeley BSIM3v3 implementation, some model parameters can be scaled depending upon actual parameter values. These parameters are U0, LU0, WU0, PU0, NPEAK, LNPEAK, WNPEAK, PNPEAK, NGATE, LNGATE, WNGATE and PNGATE.

U0, LU0, WU0 and PU0 Parameters

In the Berkeley BSIM3v3 source code, these parameters can be scaled in two routines, "b3mpar.c" and "b3set.c". In b3mpar.c the scaling is performed independently for each parameter as follows,

    if  U0 > 1 then         U0 = U0 * 1e-4;
    if  LU0 > 1 then        LU0 = LU0 * 1e-4;
    if  WU0 > 1 then        WU0 = WU0 * 1e-4;
    if  PU0 > 1 then        PU0 = PU0 * 1e-4;
	

In b3set.c the binning parameters LU0, WU0 and PU0 are scaled depending upon the U0 value.

In the SmartSpice (level 8) implementation, scaling is performed using the following rule,

    if  U0 > 1 then
        LU0 = LU0 * 1e-4;
        WU0 = WU0 * 1e-4;
        PU0 = PU0 * 1e-4;
        U0 = U0 * 1e-4;
	

i.e. parameter scaling is based upon the basic U0 value.

NPEAK, LNPEAK, WNPEAK and PNPEAK Parameters

In the SmartSpice BSIM3v3 (level 8) implementation, these parameters are scaled as follows,

    if  NPEAK > 1e20 then
        LNPEAK = LNPEAK * 1e-6
        WNPEAK = WNPEAK * 1e-6
        PNPEAK = PNPEAK * 1e-6
        NPEAK = NPEAK * 1e-6
	

NGATE, LNGATE, WNGATE and PNGATE Parameters

In the SmartSpice BSIM3v3 (level 8) implementation, these parameters are scaled as follows,

    if  NGATE > 1e23 then
        LNGATE = LNGATE * 1e-6
        WNGATE = WNGATE * 1e-6
        PNGATE = PNGATE * 1e-6
        NGATE = NGATE * 1e-6
	

3.3 Smooth Function Parameters

The SmartSpice BSIM3v3 (level 8) model contains a number of smoothing functions that were developed to eliminate discontinuities in the Berkeley BSIM3v3 model. The model parameters used in these functions are listed below;

The parameter ABULKLIM is used to prevent a discontinuity due to the limitations Abulk0 >= 0.01 and Abulk >= 0.01. The disable the Abulk smoothing function let ABULKLIM = 0.0.

The parameter NLIM is used to prevent a discontinuity for n >= 1 in the subthreshold swing parameter n equation. To disable the n smoothing function let NLIM = 0.0.

The parameter LAMBLIM is used to prevent a discontinuity for l <= 1 in the equation

(lambda) = A1 . Vgsteff + A2

and in the polysilicon depletion effect (Ngate) equation. To disable both the Lambda and Ngate smoothing functions let LAMBLIM = 0.0.

The parameter UEFFLIM is used to prevent the denominator in both the meff and Abulk equations from becoming negative. The meff smoothing function cannot be disabled.

By setting the smoothing parameter flag, SMOOTH, equal to 0, all smoothing functions except for the meff smooth- ing function will be disabled.

The capacitance model in the SmartSpice BSIM3v3 (level 8) model is evaluated in three steps.

1. The variable gate, bulk and drain charges, qg, qb and qd respectively, are calculated as functions of the gate, drain, source and bulk voltages. The charge contribution of the overlap, bulk-drain and bulk-source capacitances are not added to qg and qb at this stage. The partitioning ratio of qd to qs is determined using the XPART model parameter. Nine basic "capacitances" (partial derivatives of the qg, qd and qb charges with respect to Vgb, Vdb and Vsb) are calculated as follows;

   [EQUATION MISSING]

2. The total gate, drain and bulk charges (Qg, Qd and Qb respectively) are calculated. These charges con- tain the variable gate (qg), drain (qd) and bulk (qb) charges as well as the charge contribution of the over- lap, bulk-drain and bulk-source capacitances.

3. Sixteen derivatives of the terminal charges with respect to the terminal voltages are computed as follows;

   [EQUATION MISSING]

   where n and m are gate, source, drain or bulk.

These derivatives are used as transcapacitances for small signal AC analysis.

The following BSIM3v3 device parameters can be stored, printed and/or measured using the .save, .probe, .print and .measure statements.

• The variable transcapacitances,
  cggb
  cdgb
  cbgb
  cgdb
  cddb
  cbdb
  cgsb
  cdsb
  cbsb
  

• The variable bulk-drain and bulk-source capacitances
  capbd and capbs

• The total gate, drain and bulk charges
  Qg, Qd and Qb
  capgdo, gate-drain overlap capacitance
  capgso, gate-source overlap capacitance
  capgbo, gate-bulk overlap capacitance
  capgg, total gate capacitance
  where capgg = cggd + capgdo + capgso + capgbo
  

Note: To output capacitances during .DC analysis, let the optional parameter capdc = 1 in the .options statement.

Input Deck

	* UC Berkeley BSIM3 Version 3 Model
	* Model parameter set obtained from
	*     http://rely.eecs.berkeley.edu:8080/bsim3www/bsim3.htm

	.OPTIONS RELTOL=1e-4 ABSTOL=1e-16 VNTOL=1e-9
	.OPTIONS CAPDC=1 NUMDGT=9 FORMAT NOMOD

	.SAVE
	+  @mn1[vth]   @mn1[vdsat] @mn1[gm]    @mn1[gds]   @mn1[gmbs]
	+  @mn2[vth]   @mn2[vdsat] @mn2[gm]    @mn2[gds]   @mn2[gmbs]
	+  @mn1[cggb]  @mn1[cgdb]  @mn1[cgsb]  @mn1[cdgb]  @mn1[cddb]
	+  @mn1[cdsb]  @mn1[cbgb]  @mn1[cbdb]  @mn1[cbsb]
	+  @mn3[cggb]  @mn3[cgdb]  @mn3[cgsb]  @mn3[cdgb]  @mn3[cddb]
	+  @mn3[cdsb]  @mn3[cbgb]  @mn3[cbdb]  @mn3[cbsb]

	*===================================================================

	.DC VGG 0  5v 0.05

	Vgg gg 0 DC 3
	Vdd dd 0 DC 0
	Vbb bb 0 DC 0

	*  SmartSpice BSIM3V3 (Level 8) model; Vds=5V

	Vb   b bb  DC 0
	Vd   d dd  DC 5v
	Vs   s 0   DC 0
	Vin  g gg  DC 0

	Mn1  d g s b    NMOS w=4.0u l=0.8u
	+               PS=19.50u AS=17.10p PD=19.50u AD=17.10p

	* UC  Berkeley BSIM3v3 (Level 81) model; Vds=5V

	Vb2   b2 bb  DC 0
	Vd2   d2 dd  DC 5v
	Vs2   s2 0   DC 0
	Vin2  g2 gg  DC 0

	Mn2   d2 g2  s2  b2 NMOS81 w=4.0u l=0.8u
	+                       PS=19.50u AS=17.10p PD=19.50u AD=17.10p

	*  SmartSpice BSIM3V3 (Level 8) model; Vds=1V

	Vb3   b3 bb  DC 0
	Vd3   d3 dd  DC 1
	Vs3   s3 0   DC 0
	Vin3  g3 gg  DC 0

	Mn3   d3 g3 s3 b3  NMOS w=4.0u l=0.8u
	+                  PS=19.50u AS=17.10p PD=19.50u AD=17.10p

	* UC Berkeley BSIM3v3 (Level 81) model; Vds=1V

	Vb4   b4 bb  DC 0
	Vd4   d4 dd  DC 1
	Vs4   s4 0   DC 0
	Vin4  g4 gg  Dc 0

	MN4   d4 g4 s4 b4  NMOS81 w=4.0u l=0.8u
	+                  PS=19.50u AS=17.10p PD=19.50u AD=17.10p


	.LET kirhNplus='i(vin)+i(vs)+i(vd)+i(vb)'
	.LET kirhNminus='i(vin2)+i(vs2)+i(vd2)+i(vb2)'
	.LET kirhPplus='i(vin3)+i(vs3)+i(vd3)+i(vb3)'
	.LET kirhPminus='i(vin4)+i(vs4)+i(vd4)+i(vb4)'

	.MEASURE DC  max_kirhNplus MAX `abs(kirhNplus)'
	.MEASURE DC  max_kirhNminus MAX `abs(kirhNminus)'
	.MEASURE DC  max_kirhPplus MAX `abs(kirhPplus)'
	.MEASURE DC  max_kirhPminus MAX `abs(kirhPminus)'

	*
	****** SmartSpice BSIM3V3 (Level 8) model
	*

	.MODEL NMOS  NMOS level=8
	+ Tnom=27.0
	+ nch= 1.024685E+17  tox=1.00000E-08 xj=1.00000E-07
	+ lint= 3.75860E-08 wint=-2.02101528644562E-07
	+ vth0= .6094574   k1= .5341038  k2= 1.703463E-03  k3=-17.24589
	+ dvt0= .1767506  dvt1= .5109418  dvt2=-0.05
	+ nlx= 9.979638E-08  w0=1e-6
	+ k3b= 4.139039
	+ vsat= 97662.05  ua=-1.748481E-09  ub= 3.178541E-18 uc=1.3623e-10
	+ rdsw= 298.873  u0= 307.2991 prwb=-2.24e-4
	+ a0= .4976366
	+ keta=-2.195445E-02  a1= .0332883  a2= .9
	+ voff=-9.623903E-02  nFactor= .8408191  cit= 3.994609E-04
	+ cdsc= 1.130797E-04
	+ cdscb=2.4e-5
	+ eta0= .0145072  etab=-3.870303E-03
	+ dsub= .4116711
	+ pclm= 1.813153  pdiblc1= 2.003703E-02  pdiblc2= .00129051 pdiblcb=-1.034e-3
	+ drout= .4380235  pscbe1= 5.752058E+08  pscbe2= 7.510319E-05
	+ pvag= .6370527 prt=68.7 ngate=1.e20 alpha0=1.e-7 beta0=28.4
	+ prwg=-0.001 ags=1.2
	+ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032
	+ kt1=-.3  kt2=-.03
	+ at= 33000
	+ ute=-1.5
	+ ua1= 4.31E-09  ub1= 7.61E-18  uc1=-2.378e-10
	+ kt1l=1e-8
	+ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015
	+ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0
	+ cgdo=0.4e-9 cgso=0.4e-9
	+ clc=0.1e-6
	+ cle=0.6
	+ ckappa=0.6

	*
	***** UC Berkeley BSIM3v3 (Level 81) model
	*

	.MODEL NMOS81  nmos level=81
	+ Tnom=27.0
	+ nch= 1.024685E+17  tox=1.00000E-08 xj=1.00000E-07
	+ lint= 3.75860E-08 wint=-2.02101528644562E-07
	+ vth0= .6094574   k1= .5341038  k2= 1.703463E-03  k3=-17.24589
	+ dvt0= .1767506  dvt1= .5109418  dvt2=-0.05
	+ nlx= 9.979638E-08  w0=1e-6
	+ k3b= 4.139039
	+ vsat= 97662.05  ua=-1.748481E-09  ub= 3.178541E-18 uc=1.3623e-10
	+ rdsw= 298.873  u0= 307.2991 prwb=-2.24e-4
	+ a0= .4976366
	+ keta=-2.195445E-02  a1= .0332883  a2= .9
	+ voff=-9.623903E-02  nFactor= .8408191  cit= 3.994609E-04
	+ cdsc= 1.130797E-04
	+ cdscb=2.4e-5
	+ eta0= .0145072  etab=-3.870303E-03
	+ dsub= .4116711
	+ pclm= 1.813153  pdiblc1= 2.003703E-02  pdiblc2= .00129051 pdiblcb=-1.034e-3
	+ drout= .4380235  pscbe1= 5.752058E+08  pscbe2= 7.510319E-05
	+ pvag= .6370527 prt=68.7 ngate=1.e20 alpha0=1.e-7 beta0=28.4
	+ prwg=-0.001 ags=1.2
	+ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032
	+ kt1=-.3  kt2=-.03
	+ at= 33000
	+ ute=-1.5
	+ ua1= 4.31E-09  ub1= 7.61E-18  uc1=-2.378e-10
	+ kt1l=1e-8
	+ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015
	+ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0
	+ cgdo=0.4e-9 cgso=0.4e-9
	+ clc=0.1e-6
	+ cle=0.6
	+ ckappa=0.6

	.END
	

Measurement Results

	  * UC Berkeley BSIM3 Version 3  model

	DC Analysis, 27 deg C,Fri Mar 29 10:03:27 1996

	max_kirhnplus  =   9.051605833e-19 at=   3.700000000e+00
	max_kirhnminus =   5.000000956e-12 at=   3.250000000e+00
	max_kirhpplus  =   7.999465181e-19 at=   4.950000000e+00
	max_kirhpminus =   1.000000639e-12 at=   5.000000000e+00
	

Figure 1: Comparison of ids vs vds curves obtained using the SmartSpice BSIM3v3 level 8 and level 81 models.

This plot contains two sets of ids vs vds curves, the first obtained with vds = 5V and the second obtained with vds = 1V. As can be seen, there is no discernible difference between the curves gener- ated using the level 8 BSIM3v3 model and the original UC Berkeley BSIM3v3 model (i.e. level 81) in SmartSpice.

Figure 2 : Illustration of gm discontinuity in UC Berkeley BSIM3v3 model.

This plot contains gm vs vgs curves obtained from two transistors (mn1 and mn2). These transistors have exactly the same bias conditions. The mn1 transistor uses the SmartSpice BSIM3v3 level 8 model, while the mn2 transistor uses the original UC Berkeley model (i.e. level 81). As can be seen a discontinuity exists in the original Berkeley model and this discontinuity has been removed from the SmartSpice BSIM3v3 level 8 model.

Figure 3 : Capacitances in the SmartSpice BSIM3v3 level 8 model.

This plot contains the curves generated by some of the capacitance output variables in the Smart- Spice BSIM3v3 level 8 model.