Contents:

• Silvaco TFT Models
• RPI Amorphous TFT Model Level=35 in SmartSpice
  • RPI Amorphous TFT Model Version=1
  • RPI Amorphous TFT Model Parameters (Level=35)
  • Device Characterization
  • A-Si RPI TFT Model (Version=1 & Version=2)
  • A-Si RPI Model (Level=35 & Version=1)
  • A-Si RPI Model (Level=35 & Version=1 Fitting Results)
• RPI PolySilicon TFT Model Level=36 in SmartSpice
  • RPI PolySilicon TFT Model Level=36
  • RPI PolySilicon TFT Model Version=1
  • RPI PolySilicon TFT Model Version=2
  • RPI PolySilicon TFT Model Version=1 & Version=2
  • RPI PolySilicon TFT Model Version=2
  • RPI PolySilicon TFT Model Version=1
  • RPI PolySilicon TFT Model Version=1 & Version=2
  • RPI PolySilicon TFT Model Version=2
  • RPI PolySilicon TFT Model Version=1 & Version=2
  • Device Characterization
  • RPI PolySilicon TFT Model Version=2 +RPISCALE=1
• SmartSpice Analog Circuit Simulator
  • SmartSpice Specail Options and Binning Model
  • SmartSpice - Outline
  • Gateway - Schematic Capture
  • Support Models in SmartSpice
  • High Voltage Model (Level=88) Silvaco Only!!
  • SmartSpice Advantage
  • SmartSpice Advantage - SmartSpice Convergence
  • Simulation Verification with SmartSpice
• Conclusion

Download full presentation 11Mb pdf)