Silos - Leader in Digital Verilog Simulation

Contents

  • Introduction
    • What is SILOS
    • Digital Flow
    • History of SILOS
    • SILOS Platforms
    • SILOS Markets
  • Starting SILOS Project
    • Starting SILOS
    • Opening a Project
    • Create a Project
    • Project Files
    • Starting a Simulation
    • Output of a Simulation
  • Explorer and Analyzer
    • Explorer - Symbols
    • Explorer - Context Menu
  • Source Code Debugging
    • Source Code Waveforms
    • Rearranging Signal - Drag and Drop
    • Show Source Code
    • Visual Debug
      • Time Point for Tracing Signal
      • Trace Signal Inputs
      • Status Window
      • "pad"
      • "stimulus.pad"
      • "reset"
    • Report Generation
    • Vector Display
  • State Machine Design Entry
    • State Machine Values
    • Waveform Annotation
    • Grouping Waveforms
    • Conditional Search
    • Data Analyzer
      • Scan Buttons
      • Timescale
      • Scale to Value
      • Pan Buttons
    • Data Tips
  • Advanced Debugging Features
    • Single Stepping
    • Set and Force
    • Breakpoints
    • Code Coverage
    • Operator Code Coverage
    • Merging Code Coverage
  • Finite State Machine Example
    • Finite State Machine (FSM) Entry
    • FSM Entry - Transition Mode
    • FSM Entry - Notes
    • FSM Debugging
    • FSM Debugging - FSM Window
  • Gate Level Debugging
    • Resize Interface
    • Buffer Gate
      • "qqbar"
      • "o3"
      • "ck"
    • Errors
    • Analog Waveforms
    • SILOS Advanced Features
    • SILOS Future - Analog Mixed-Signal Solution
    • Analog and Mixed Signal Design Flow

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