Contents:

• Introduction
• Input
• Masks
• MAP File
• INPUT File
• Annotated/Modified Map File
• Device Net List
• INPUT File
• 3D-Structure File
• Gate Fringing Capacitance
• Extrinsic Capacitance: Fringing Capacitance
• Parasitic Netlist
• Realistic Processing
• SEM Photograph of Typical Interconnect Geometry
• Realistic Processing
• Parasitic Netlist
• Realistic Processing
• SPICE Simulation
• Conclusion

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