Hints, Tips and Solutions - November 2006
Q. Is it possible to calculate the resistance components of a MOSFET (i.e. channel resistance, epi resistance, substrate resistance etc.) as a function of gate bias?
A. The resistance components of a MOSFET, Trench UMOS or LDMOS device can in general be obtained from the quasi-Fermi level potential and the terminal current.
To illustrate the resistance calculation, the standard example “mosfetex01.in” was used. A structure file is saved at a drain voltage of 0.1V and a gate voltage of 3V. In TonyPlot, plot the Net Doping contour as well as the Electrodes. Using the Cutline tool, do a horizontal cut across the device along the channel from the source to the drain.
Then using the “Function” options create a function that is defined by the electron QFL divided by the drain bias at the operating point. The drain bias is a constant that can be taken from either the run-time output or a plot of the log file. Plotting this function will give the cumulative resistance along the channel from the source to the drain.
You may also want to determine the channel resistance as a function of gate bias. To do this you can use the EXTRACT and PROBE statements as follows:
First, use the EXTRACT statement to obtain the locations of the junction edges. The following lines show how to obtain the locations of the junction edges 0.01 microns below the oxide interface.
go atlas
# Find out the y location of the oxide interface
extract init infile=”mos1ex01_0.str”
extract name=”xj_y” min.bound y.pos
material=Silicon” x.val=0.5 y.val=0.5
#
# set the location to 0.01 microns below the interface
set xj_y=$xj_y+0.01
# find the locations of the junction edges
extract init infile=mos1ex01_0.str”
extrace name=”xj1” xj material=”Silicon”
mat.occno=1 y.val=$sj_j junc.occno=1
extrace name=”xj2” xj material=”Silicon”
mat.occno=1 y.val=$sj_j junc.occno=2
Now the PROBE statement can be used to determine the values of the electron QFL at the two junctions. The following lines show how to extract the electron QFL values as a function of gate bias.
probe name=”ch1” x=$xj1 y=$xj_y qfn
probe name=”ch2” x=$xj2 y=$xj_y qfn
# ramp gate
log outf=mos1ex01_1.log master
solve vgate=0 vstep=0.05 vfinal=3.0 name=gate
Finally, you can extract the channel resistance as a function of gate bias.
extract infile=”mos1ex01_1.log”
extract name=”id” max(curve(v.”gate”,i,”drain”))
extract name=”Rch” curve(v.”gate”,abs(probe.”ch1”-probe.”ch2”)/$id)
outf=”rch.dat”
Figure 1. Target MOSFET device structure and resistance distribution
along the gate channel cutline(0,0.22)-(1.2, 0.22)
Figure 2. Channel Resistance and IdVg curve.