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Simulation Standard - 1998

 


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Volume 9, Number 1, January 1998

Local Optimization Templates for Extracting BSIMv3v3.1 Pramaeters in UTMOST III

The SmartSpice Interface to Cadence (revisited)

CellRATER from Tavern Technology

Cell Characterization with MODIF Statement in SmartSpice

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Volume 9, Number 3, March 1998

Savage Enhanced with Recognition and Reporting of Hierarchical Structure of Errors

Scanbox Approach to Shape Reconstruction for Automated Reticle Inspection

Circuit Verification via Hypergraph Realization

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Volume 9, Number 4, April 1998

BSIM3SOI - Level=25 Model Released in SmartSpice

Release of Upgraded SmartSpice Interface to Cadence

Advanced Cell Characterization Using SmartSpice Scripting Features

UTMOST Log File Conversion for TonyPlot

Release of RPI Amorphous Silicon and Polysilicon TFT Models in SmartSpice and UTMOST

Spice Model Validation

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Volume 9, Number 6, June 1998

Maverick: Hierarchical Netlist Extractor for PC Platforms

Optimum Standard Cell Layout Using Weighted Cycle Linear Placement

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Volume 9, Number 7, July 1998

BSIM3v3.2 Model Released in SmartSpice and UTMOST III

EkV MOSFET Model Version 2.6 Now Available in SmartSpice and UTMOST

SmartSpice v.1.5.5 Release Notes

UTMOST File Format Explosion

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Volume 9, Number 9, September 1998

Real- time DRC in Expert Layout Editor

Recursive Cutting of Rectangular Partitions for VLSI Floorplanning

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Volume 9, Number 10, October 1998

Parallel ALTER Statements in SmartSpice

Philips Model 9: New MM9 Extraction Routine in UTMOST III

Scholar - An Advanced Hierarchical Schematic Capture

SPAYN - Recent Developments

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Volume 9, Number 12, December 1998

Expert Expanded with Client-Server Project/Library Management

LISA

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