Simulation Standard - 1997

PDF	Volume 8, Number 1, January 1997 Flicker Noise Measurement and SPICE Parameter Extractionfor Modeling and Characterization Service (Part 2) Fundamental Improvements in BSIM3v3.1 Model (Available in SmartSpice) Automated Model Binning Hints & Tips
PDF	Volume 8, Number 3, March 1997 UCSD HBT SmartSpice Model Released! Measuring Ring Oscillator Time Delay for CMOS, SOI and TFT Technologies Improved and Expanded Reedholm Interface to UTMOST Simulation of SOI Analog Circuits with SmartSpice Simulation and Optimization of CMOS Noise Parameter (Part III) Further Automation of Worst-Case SPICE Model Library Generation New Release of PC SmartSpice Diagnose Process Variations By Using SPC Charts and a Wafer Map Diagnose Process Variations By Using Wafer Map and Highlighted Histogram Plot Hints & Tips
PDF	Volume 8, Number 4, April 1997 QUANTUM: Quantum Mechanical Simulator Released in ATLAS SIMS-Verified Implant Models Released in ATHENA 4.3 Modifications and Additions to the Ferroelectric Model in ATLAS Hints & Tips
PDF	Volume 8, Number 6, June 1997 CLEVER - Process Technology Based Extraction and Optimization of Custom Cell Parasitics EXACT - Process Technology Based Interconnect Parasitic Library Generation Blaze Simulation of SiGe:Si Heterostructure p-MOSFETs Hints & Tips
PDF	Volume 8, Number 7, July 1997 Custom Implementation of Noise Models Using the SmartSpice Interpreter An Efficient Use of Threads for SmartSpice Parallelization Trouble-Shooting GPIB Communication Problems Generation of a New SPAYN Database from a Limited Data Set Hints & Tips
PDF	Volume 8, Number 9, September 1997 Introducing Expert ULSI Layout Processor for PC-based Platforms Chip Navigation in Expert Introducing Savage - Efficient Design Rule Checker for PC-based Platforms Generalized Convexity Approach to Cell Boundary Shape Approximation Hints & Tips
PDF	Volume 8, Number 10, October 1997 SmartLib: Product-Independent SPICE Model Library Parallel SmartSpice for PC BSIM3v3.1 Intrinsic Capacitance Modeling in UTMOST A New C-Interpreter RPI Polysilicon and Amorphous TFT Implemented in SmartSpice
PDF	Volume 8, Number 12, December 1997 Expert - PC NT Layout Editor Minimal Area Design of Power/Ground Nets Application of Scan Line Methodology to Perform Metric Operations in DRC Hints & Tips