Passive Element and Cell/Chip Level Parasitic Extraction Services provide solutions for customers who have occasional cell level passive element and parasitic modeling requirements or have a need for integrated IC CAD/extraction solutions. All extractions are physics-based—not rule based, so novel structures can be analyzed accurately for all coupling effects. Simucad products EXACT and QUEST are used for Passive Element Extraction Services. CLEVER and STELLAR products are used for Cell/Chip Level Extraction Services.

Benefits

• Removes the requirement for expensive, full-time, in-house engineers for intermittent passive and cell level parasitic extractions

• Provides access to highly qualified engineers in the field of semiconductor physics, parasitic extraction, and commercial EDA flows

• Removes requirement for employee re-training

• Models are all based on device physics, so even novel devices can be correctly modeled for frequency dependent inductance, resistance and capacitance

 

Interconnect Parasitic Capacitance Coefficient Extraction Service

We use Simucad’s EXACT – Interconnect Parasitic Coefficient Generation package to deliver the most accurate interconnect models for nanometer semiconductor processes and generate layout parameter extraction (LPE) rule files for leading full chip extraction tools. EXACT uses powerful 3D field solver technology.

 

Deliverables

• Customer – process parameters, optional GDSII test structures

• Simucad – xCalibre™, Calibre xRC™, HIPEX, Diva™, and Dracula™ LPE parasitic extraction runsets
  
  

Example of a 3D test structure created and used in EXACT.

 

A typical deliverable – a section of Mentor Graphics xCalibre/Calibre xRC rule file generated by EXACT.

 

RF Passive Element Characterization Service

We use Simucad’s Quest – High Frequency Parasitic Extractor for:

• 2-port inductor analysis providing frequency dependent or frequency independent SPICE inductor models at gigahertz frequencies

• Multi-port S, Y or Z parameter analysis of passive elements, W-element Transmission Line SPICE model extraction

• Turnkey optimized inductor library generation based on your process capabilities and desired range of inductances (delivery includes GDSII)

 

Deliverables

• Customer – process parameters, field solver parameters, GDSII of inductors

• Simucad – frequency dependent inductor models, multi-port S parameters, W-element transmission line elements, RLCG and Q factor data files, 3D structure files, interactive 2D and 3D graphics
  

 

 

High Accurate Bit Cell RC Extraction Service

We use Simucad’s CLEVER – Physics-Based Parasitic Extractor for:

• Cell level field solver provides automated resistance and capacitance inter-connect parasitics, back-annotated onto extracted SPICE netlist

• 3D structures RC modeled using opto-lithographic simulator to include photo-resist corner rounding

• Masks containing Optical Proximity Correction (OPC) are correctly modeled

• Realistic deposition and etch processing included in RC extraction to create the most realistic 3D model possible of the device structure prior to field solving resulting in the highest possible level of extracted parasitic accuracy

 

Deliverables

• Customer – process parameters, GDSII of cells

• Simucad – SPICE netlist with active devices and RC parasitics, annotated layout file showing active device connections, interactive 2D and 3D graphics

 

 

 

Cell/Block Parasitic Capacitance Extraction Service

We use Simucad’s STELLAR – Characterization of Cell/Block Parasitics for:

• High accuracy netlist extraction of standard cell libraries, IO libraries, memories and custom blocks including capacitances

 

Deliverables

• Customer – process parameters, GDSII of cells/blocks

• Simucad – SPICE netlist with active devices and C parasitics, interactive 2D and 3D graphics
  

 

• Performing 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology

• HIPEX is tightly integrated with the Expert Layout Editor for the complete design flow of DRC/LVS/LPE and RC parasitic extraction on one platform
  

• Customer – technology file (Raphael™ or process parameters for EXACT to create tech file), GDSII of chip

• Simucad – SPICE netlist with active devices and C parasitics