HyperFault
Mixed-Level Fault Simulator

HyperFault is a Verilog IEEE-1364-2001 compliant fault simulator that analyzes test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing.

Key Features

• Verilog HDL IEEE 1364-2001 compliant fault simulator
  
• Uses standard Verilog source files and libraries for mixed-level fault simulation with gate, behavioral and switch devices
  
• Complements BIST and ATPG in finding interconnect faults
  
• Efficient multi-pass concurrent fault simulation algorithm with iterative fault collapsing gives optimal memory allocation and excellent runtime performance
  
• Automatic design partitioning supports distributed CPUs with load balancing for fast grading of large designs
  
• Fault grading models include stuck-at high/low output and input faults
  
• Full timing fault simulation supports SDF back annotation for post-route delay analysis

Rev 102207_12