Expert 90-day Roadmap - August 2008

Processing external pin order to support matched I/O ports between schematic and layout netlist.

Pcell local caching

JavaScript support for Pcells and design automation

Callback function for Pcells

Compare an ECO netlist with the existing layout and then display physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the discrepancies and match the layout back to the schematic.

Schematic Driven Layout. Use relative schematic position and transformation info from Gateway to create initial device placement.

Schematic Driven Layout. Backannotation from SDL generated layout to schematic view

Tabbed browser user-interface for multiple cellview windows .

Include basic design rules in Expert technology

Warning about potential rule violations before they are created through distance display

Automatically snap cursor to the right location to fit minimum design rules

Include layer generation scripts, parasitic extraction rules, and Guardian NET external LISA files information into Expert technology file