AccuCore
Block Characterization and Modeling With STA

AccuCore performs timing characterization of multi-million device circuits with SmartSpice accuracy and performs block and full-chip Static Timing Analysis (STA) on multi-million gate designs.

Key Features

• Generates Liberty™ (.lib) timing models, generates a gate-level verilog netlist and generates or reads DSPF files for STA
• Exports fully sensitized SPICE deck for selected critical paths and clocktrees with measurements
• Automatically partitions blocks into cells
• Automatically extracts cell functions and generates vectors required for accurate SPICE characterization
• Includes fast API-based SmartSpice characterization engine
• Complete block and full-chip gate-level STA environment for rapid bottleneck analysis and timing verification
• Powerful command set enables mixing both custom and ASIC/SoC functions in a single analysis environment

Rev 011808_16