HIPEX
FULL-CHIP PARASITIC EXTRACTION

HIPEX is an accurate and fast full-chip hierarchical extraction software that performs extraction of parasitic capacitances and resistances from hierarchical layouts. HIPEX is tightly integrated with the Expert Layout Editor for complete design flow of DRC/LVS and RC parasitic extraction.

Key Features

• Multiple parasitic extraction models, including lumped RC, C only, R only, coupled C and fully distributed RC
  
• Selected net extraction for fast RC extraction of critical path nets in SoCs and large memories
  
• Efficient network reduction for distributed parasitic RC networks
  
• Output parasitic netlist files in SPICE, back-annotated netlist, DSPF and SPEF formats
  
• Automated back annotation enables accurate post-layout simulation and analysis
  
• Parasitic device extraction on both transistor and gate levels

Rev. 010509_20