Guardian
DRC/LVS/NET Physical Verification

Guardian provides interactive and batch mode verification of analog, mixed signal and RF IC designs. Integrated with Simucad's schematic capture and layout editor. Guardian efficiently performs design rule checks (DRC) and layout vs. schematic (LVS) comparisons.

Key Features

Integration with Expert Layout and Gateway Schematic Editors provides a complete entry-to-verification design flow for analog, mixed-signal and RF designs
Supports DRC/LVS/NET rule files translated from Calibre™, Dracula™, and Diva™
Broad support of semiconductor process technologies through foundry-proven process design kits (PDKs)
Fast, intuitive and hierarchical LVS debugging with cross-probing to layout and schematic views
Guardian NET supports stress effects and well proximity parameter extraction