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SmartSpice
The New Gold Standard Analog Circuit Simulator

SmartSpice delivers the highest performance and accuracy required to design complex high precision analog circuits, analog mixed-signal circuits, analyze critical nets, characterize cell libraries, etc.. SmartSpice is compatible with popular analog design flows and foundry-supplied device models.

Key Features

• 100% HSPICE™ and SPECTRE™ compatible for netlists, models, analysis features, and results
• Provides the most accurate circuit simulation results for critical analog designs
   
• Offers largest capacity of any true SPICE circuit simulator – up to 400 thousand active devices in 32-bit and 8 million active devices in 64-bit version
• Fastest run-time of any true SPICE circuit simulator and the only SPICE supporting multiple threads for parallel operation
• Multiple solvers and stepping algorithms for robust convergence
• Largest collection of calibrated SPICE models for traditional technologies (Bipolar, CMOS) and emerging technologies (TFT, SOI, HBT, FRAM, etc.)
• Provides open model development environment and extensive analog behavioral capability with Verilog-A
   
• Enables SEE (Single Event Effects) reliability analysis for nanometer scale designs

 

Accuracy: SmartSpice is the most accurate circuit simulator for critical analog designs incorporating nanometer effects

• Uses Gaussian elimination in an efficient matrix (based on the original Berkeley 3C1 solver)
• A library of solvers to enhance the solution of linear equations (3 direct and 2 iterative solvers)
• Verifies and validates Berkeley physics-based model parameters at run-time for continuity, linearity, and valid parameter range
• Detects inconsistencies in poorly-extracted foundry models and prevents these errors from degrading the final product performance and accuracy
• The simulator of choice at foundries that focus on analog and mixed-signal process accuracy
• Offers a full set of options for controlling speed vs. accuracy of simulations

 

Capacity: SmartSpice simulates more active devices than any other analog circuit simulator

• Simulates circuits up to 400K active devices (limited by OS addressable memory)
• SmartSpice-64 supports simulation of an unprecedented 8 million active devices with full SPICE accuracy on 64-bit workstations

 

SmartSpice-64 offers true SPICE accuracy for simulating full chip static, dynamic, and leakage power or for signal integrity of clock trees with extracted parasitics and victim/aggressor nets.

 

 

Speed: SmartSpice runs faster than other true SPICE simulators

• Simulates at 2 to 4 times the raw speed of other SPICE products
• Supports multiple parallel 32/64-bit CPUs for near-logarithmic multi-threaded operation
• Distributed SmartSpice and remote .ALTER
• Effective parallelization using pool of threads

 

Convergence: SmartSpice selects the right solver for optimal convergence integrity, speed, and stability

• Surveys initial conditions and iteratively sequences through a series of methods and algorithms to attain optimal convergence
• Multiple solvers provide the best solver for a given circuit topology
• Offers multiple options for supporting convergence for any given solver

Analysis: SmartSpice offers user-defined support for analysis options• Stop/Continue Algorithm for transient analysis

• Nested parametric analysis
• Scoping of names used in netlist
• Fast cell characterization via direct matrix access on the next parametric step
• Sophisticated optimization at the sub-circuit level
   
• SEE analysis using .RAD statement leveraging foundry supplied compact models
   
• Equation editor for .MODEL parameters to support sub 65 nanometer designs

 

Ease of Adoption: SmartSpice fits your design flow and foundry models

• Supports foundry-supplied SmartSpice, HSPICE and SPECTRE models
   
• Supports legacy netlists from HSPICE, PSPICE™, and Berkeley SPICE
• Seamless integration with Cadence analog environment through OASIS (IC4.4.6, IC5.0, IC5.032, Solaris, IC5.032, and Linux supported; IC5.033 Linux and Solaris in testing)
• Total integration with Simucad Custom IC CAD tool flow

 

Model Development Capabilities

• Core competence in SPICE modeling, data acquisition and model parameter extraction since 1984 with UTMOST for the highest accuracy in analog models
• Verilog-A models offer fastest method for implementing Accelera standard electric-thermal models, sensor models, and other mixed physical effects
• C-Interpreter enables modeling engineers to quickly interpret and debug models external to SmartSpice
• Simucad offers accurate and prompt SPICE Modeling Services to extract DC, AC, S-parameters, capacitance, temperature, noise, and SPICE parameters over full temperature and corner models using statistical analysis

Transient noise simulation: Voltage and noise waveforms at 2 different circuit nodes.

 

Models Available

BJT/HBT:	Gummel-Poon, Quasi-RC, VBIC, MEXTRAM, MODELLA, HiCUM
MOSFET:	LEVEL 1, LEVEL 2, LEVEL 3, BSIM1, BSIM3, BSIM4, MOS 20, EKV, HiSIM, PSP, LEVEL 88, HiSIM HV
TFT:	LEVEl 35, LEVEL 36
SOI:	Berkeley BSIM3SOI PD/DD/FD, LETISOI
MESFET:	Stats, Curtice I & II, TriQuint
JFET:	LEVEL 1, LEVEL 2
Diode:	Berkeley, Fowler-Nordheim, Philips JUNCAP/Level 500
FRAM:	Ramtron FCAP

Inputs
Berkeley SPICE netlist, HSPICE netlist, W-element RLGC matrix files, S-parameter model files, Verilog-A and AMS, C/C++
 
Outputs
Rawfiles, output listings, Analysis results, Measurement data, (portable across unix/windows platforms)

 

 

Rev 010509_34