Roadmap

SmartSpice 90 Day Development Roadmap, February 2010

SmartSpice core

  • .biaschk support for geometry and other variables in condition statement
  • Parser performance/memory optimization in hierarchical mode

HSIM compatibility

  • Support Circuit Check functionality

HSPICE compatibility

  • Develop MOS Reliability Analysis (MOSRA): hot-carrier injection (HCI) analysis
  • Develop .MATERIAL analysis for W-element
  • Improve performance of .lib, .del lib for .ALTER statement
  • Support spatial variation in VARIATION block
  • Develop AC match analysis
  • Support .option MODMONTE
  • Support VSRC Linear Feedback Shift Register (LFSR)

SPECTRE compatibility

  • Support DC/AC match analysis
  • Support of argument "oprobe" in the noise analysis statement
  • Support of "skipdc" statement
  • Support of "if-else-endif" statements

Model Reliability

  • Improve SmartSpice CAS degradation API design

Verilog A

  • Improve Verilog-A model multi-threading support
  • Enhance VADebugger to support multi-module debugging
  • Enhance parser to protect Verilog-A source code from being revealed
  • Enhance parser to support digital constants in the analog blocks

SmartView

  • Continue adding digital viewing capabilities
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