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Harmony 90-day Roadmap – August 2008

Continue Verilog-A speed and memory usage improvements
Finish Verilog-A ddt and idt operator update
Enable visual debug feature for 64-bit platforms
Verilog-A functionality upgrades
Support Spice SWEEP option
Add 'default_nettype none' Verilog feature
Add Spice node voltages to VCD output file

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