Verilog-A
Language for SmartSpice

Interpreted or compiled Verilog-A language combined with SmartSpice provides circuit designers and model developers with an easy-to-use, comprehensive environment for the design and verification of complex analog and mixed-signal circuits and models.

Key Features

• SmartSpice Verilog-A is within 2x runtime performance of C-compiled ADMS models
  
• Supports top-down design via behavioral modeling and bottom-up verification of analog and mixed-signal designs
• Enables compact model engineers to easily develop proprietary models for any semiconductor technology
• Enables executable specification to connect analog and digital engineers in a single design project
• Support for encrypting Verilog-A source allows distribution of proprietary models without disclosure
• Verilog-A is shipped as an included element of SIMUCAD MODELLIB libraries
• Provides secure, transportable method for analog IP distribution and evaluation

Rev. 082009_29