ModelLib Dynamically-Linked SPICE Models
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HV MOS
BSIM3-based High Voltage Compact Model
HiSIM HV
Surface Potential Based HV and LDMOS Compact Model
BSIM3v3.2.4
Industry Standard
Sub-0.13 Micron
MOSFET Model
BSIMMG
Berkeley Common Multi-Gate Transistor Model
BSIM3SOIv3.2
Industry Standard
SOI Model
BSIM4v4
Industry Standard
Sub-0.13 Micron
MOSFET Model
EKV
Low Power
MOSFET Model
HICUM
High Speed
Bipolar Model
HiSIM
Surface Potential-
Based MOSFET Model
Mextram
General Purpose
Bipolar Model
Modella
Lateral PNP
Bipolar Model
Mosvar
PSP-Based MOS
Varactor Model
UOTFT
Universal Organic TFT Model
VBIC
Advanced BJT and HBT Model
The PSP model is a compact MOSFET model which has been jointly developed by Philips Research and Penn State University.
PSP is a surface-potential based MOS Model, containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping gradient effects, STI stress, etc.) necessary to model present-day and deep-submicron bulk CMOS technologies.
PSP model characteristics are:
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Figure 1: Output characteristics of 0.36/0.09 µm
MOS-FET; Vgs varies between 0.5 and 1V, Vsb=0. Circles represent measured
data, solid lines correspond to PSP. |
General Features of PSP Model
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Figure 2: Gate tunneling current; Vsb=0V,
Vds=0.025, 0.042, 0.61and 1V |
Model Highlights
The PSP model is a symmetrical, surface-potential-based model, giving an accurate physical description of the transition from weak to strong inversion. The PSP model includes an accurate description of all physical effects important for modern and future CMOS technologies, such as:
In addition, PSP gives an accurate description of charges and currents and their first-order derivatives (transconductance, conductance, capacitances), but also of their higher-order derivatives. This yields to an accurate description of MOSFET distortion behavior, making the PSP model well suited for digital, analog as well as RF circuit design.
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Figure 3: MOSFET transfer characteristics; Vds=25mV,
Vsb=0, 0.2...1.0V |
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Figure 4: Output conductance; Vgs varies
between 0.5 and 1V, Vsb = 0 |
Simucad Implementation
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Figure 5: Measured (symbols) and modelled (lines)
input capacitance Cgg as a function of gate bias Vgs
for W/L=800µm/90nm n-channel MOSFET; Vds=0, Vsb=0 |
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Figure 6: Drain (Sid) and gate (Sig)
current noise spectral density versus gate-source bias for an L=90 nm
n-channel device. Symbols denote measurements and lines represent modelled
results using PSP. |
Reference: G.Gildenblat et alii. “Introduction to PSP”;
(presented at the 2005 Workshop on Compact modeling in Annaheim CA, May 2005;
Technical Proceedings, pp. 19-24)
Rev. 101807_02
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