Employment Opportunity

Job title Verilog/VHDL Simulator Developers
Location(s) Santa Clara, CA
Description Aggressively develop next-generation, Verilog/VHDL simulator. Work in a core team of elite software developers (coders) to develop and document state-of-the-art simulators. 
 
Requirements

A successful candidate must have the following experience:

  • Minimum MS in CS/EE with at least 5 years of relevant Verilog simulator development experience.
  • Must be highly proficient with C/C++, different operating systems and software development processes.

 

Apply by email Please quote ref. SW-VVHDL-CA when applying
jobs@simucad.com
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